(1) Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof. More particularly, the present invention relates to a semiconductor device which includes at least two kinds of field-effect transistors having different threshold voltages integrated on a compound semiconductor substrate, and to a manufacturing method thereof.
(2) Description of the Related Arts
Field effect transistors formed on semi-insulating substrates made of GaAs (hereinafter referred to as GaAsFET) have been used for power amplifiers or switches of communication devices, especially mobile telephone terminals, due to its high performance. Particularly, monolithic microwave integrated circuits (hereinafter referred to as MMIC) in which active elements such as the GaAsFET and passive elements such as a resistance element and a capacitance element are integrated thereon have been widely in practical use.
In recent years, higher performance in the above-described GaAsMMIC has been demanded. Thus, the GaAsMMIC which includes the aforementioned power amplifiers and switches structured by a depletion-mode field-effect transistor (hereinafter referred to as D-FET) and a logic circuit structured by an enhancement-mode field-effect transistor (hereinafter referred to as E-FET), in other words, an E/D-FET in which the E-FET and the D-FET are both mounted on the same substrate is in demand.
Examples of conventional E/D-FETs include the semiconductor device disclosed in Patent reference 1: Japanese Unexamined Patent Application Publication NO. 8-116034 and the semiconductor device disclosed in Patent reference 2: Japanese Patent NO. 3483716.
First, a conventional semiconductor device disclosed in Patent reference 1 will be described. FIG. 1 is a sectional view which illustrates a structure of the semiconductor device disclosed in Patent reference 1.
A semiconductor device 300 illustrated in FIG. 1 includes an E-FET region 31 in which an E-FET is formed and a D-FET region 32 in which a D-FET is formed. The semiconductor device 300 includes: a semiconductor substrate 301 made of semi-insulating GaAs, a buffer layer 302, a channel layer 303, a donor layer 304, a threshold adjustment layer 305, an etching stopper layer 306, a contact layer 307, an isolation region 308, an insulating film 309, a sidewall insulating films 312, gate electrodes 314 and 315, and ohmic electrodes 316.
The buffer layer 302 is made of undoped GaAs and formed on the semiconductor substrate 301. The channel layer 303 is made of undoped InGaAs and formed on the buffer layer 302. The donor layer 304 is made of n-type AlGaAs and formed on the channel layer 303. The threshold adjustment layer 305 is made of n-type GaAs and formed on the donor layer 304. The etching stopper layer 306 is made of n-type AlGaAs and formed on the threshold adjustment layer 305. The contact layer 307 is made of n-type GaAs and formed on the etching stopper layer 306. The isolation region 308 is formed through ion implantation and electrically isolates the E-FET region 31 from the D-FET region 32. The insulating film 309 is made using silicon dioxide film and formed on the contact layer 307. The gate electrode 314 forms a Schottky barrier junction with the donor layer 304. The gate electrode 315 forms a Schottky barrier junction with the etching stopper layer 306. The sidewall insulating films 312 are made using silicon dioxide film and isolate the contact layer 307 from the gate electrode 314 or from the gate electrode 315. The ohmic electrodes 316 are formed in openings defined in the insulating film 309, each of which is electrically connected to the contact layer 307.
A method of manufacturing the conventional semiconductor device 300 will be described next. FIGS. 2A to 2E illustrate sectional structures in a manufacturing process of the semiconductor device 300.
First, on the semiconductor substrate 301 made of semi-insulating GaAs, the GaAs buffer layer 302, the InGaAs channel layer 303, the AlGaAs donor layer 304, the GaAs threshold adjustment layer 305, the AlGaAs etching stopper layer 306 and the GaAs contact layer 307 are sequentially epitaxially grown through a metal organic chemical vapor deposition (hereinafter referred to as MOCVD) method, a molecular beam epitaxy (hereinafter referred to as MBE) method, and the like. The isolation region 308 is formed by implanting boron ions, so that the E-FET region 31 and the D-FET region 32 are separated. Through the steps described above, the structure illustrated in FIG. 2A is formed.
Next, the insulating film 309 is made using silicon dioxide film, and then a portion of the insulating film 309 for defining a gate opening is removed through selective dry-etching by using a photoresist mask (not illustrated), so that the contact layer 307 is exposed. Further, the exposed portion of the contact layer 307 is removed through selective dry-etching, so that the etching stopper layer 306 is exposed and gate openings 310 and 311 are defined. Through the steps described above, the structure illustrated in FIG. 2B is formed.
Next, the insulating film made using silicon dioxide film is formed on the gate openings 310 and 311, and then etched back through dry etching, so that the sidewall insulating films 312 are formed. Through the steps described above, the structure illustrated in FIG. 2C is formed.
Next, the gate opening 311 is covered with a photoresist mask (not illustrated), and the etching stopper layer 306 exposed in the gate opening 310 is removed through wet-etching using phosphate etchant, so that the threshold adjustment layer 305 is exposed. Further, the exposed threshold adjustment layer 305 is removed through selective dry-etching, so that the donor layer 304 is exposed and a gate opening 313 is formed. Through the steps described above, the structure illustrated in FIG. 2D is formed.
Next, a photoresist pattern is removed and WSi and W are laminated and then removed, leaving a portion to be a gate electrode, through dry-etching by using a photoresist mask (not illustrated), so that the E-FET gate electrode 314 and the D-FET gate electrode 315 are simultaneously formed. Through the steps described above, the structure illustrated in FIG. 2E is formed.
Next, an opening in which an ohmic electrode is to be formed is defined in the insulating film 309 by using a photoresist mask (not illustrated), and the ohmic electrode 316 made of AuGeNi is formed through the vacuum evaporation and lift-off method. Through the steps described above, the structure of the conventional semiconductor device 300 illustrated in FIG. 1 is formed.
Next, a conventional semiconductor device disclosed in Patent reference 2 will be described.
FIG. 3 is a sectional view which illustrates a structure of the semiconductor device disclosed in Patent reference 2.
A semiconductor device 400 illustrated in FIG. 3 includes an E-FET region 41 in which an E-FET is formed and a D-FET region 42 in which a D-FET is formed. The semiconductor device 400 includes: a semiconductor substrate 401 made of semi-insulating GaAs; a buffer layer 402; a channel layer 403; a donor layer 404; a threshold adjustment layer 405; a contact layer 406; an isolation region 407; an insulating film 409; gate electrodes 412 and 413; and ohmic electrodes 414.
The structure illustrated in FIG. 3 is different from the structure illustrated in FIG. 1, mainly in that the threshold adjustment layer 405 is included in place of the threshold adjustment layer 305 and the etching stopper layer 306. The single threshold adjustment layer 405 made of InGaP serves as the threshold adjustment layer 305 adjusting the threshold voltage and the etching stopper layer 306 to function as a stopper during the etching. Further difference is that the sidewall insulating films 312 are eliminated. A recess opening 408 and the insulating film 409 are provided for avoiding contact between the gate electrodes 412 and 413 and the contact layer 406 in FIG. 3, whereas the sidewall insulating films 312 are provided for avoiding contact between the gate electrodes 314 and 315 and the contact layer 307 in FIG. 1.
The semiconductor substrate 301, the buffer layer 302, the channel layer 303, the donor layer 304, the contact layer 307, the isolation region 308, the insulating film 309, the gate electrode 314, the gate electrode 315, and the ohmic electrode 316 correspond to the semiconductor substrate 401, the buffer layer 402, the channel layer 403, the donor layer 404, the contact layer 406, the isolation region 407, the insulating film 409, the gate electrode 412, the gate electrode 413, and the ohmic electrode 414, respectively.
Hereinafter, descriptions focus on the differences, omitting the same points. The threshold adjustment layer 405 is made of n-type InGaP and formed on the donor layer 404. The gate electrode 413 forms a Schottky barrier junction with the threshold adjustment layer 405.
A method of manufacturing the conventional semiconductor device 400 will be described next. FIGS. 4A to 4E illustrate sectional structures in a manufacturing process of the semiconductor device 400.
First, on the semiconductor substrate 401 made of semi-insulating GaAs, the GaAs buffer layer 402, the InGaAs channel layer 403, the AlGaAs donor layer 404, the InGaP threshold adjustment layer 405, the GaAs contact layer 406 are sequentially epitaxially grown through a MOCVD method, a MBE method, and the like. The isolation region 407 is formed by implanting hydrogen ions using a photoresist mask (not illustrated), so that the E-FET region 41 and the D-FET region 42 are separated. Through the steps described above, the structure illustrated in FIG. 4A is formed.
Next, predetermined portions in the contact layer 406 are removed through selective wet-etching using tartaric acid series etchant by using a photoresist mask (not illustrated), so that the threshold adjustment layer 405 is exposed and recess openings 408 are defined. Through the steps described above, the structure illustrated in FIG. 4B is formed.
Next, the insulating film 409 made using silicon dioxide film is formed, and then portions for forming gate electrodes in the insulating film 409 are removed through selective dry-etching by using a photoresist mask (not illustrated), so that the threshold adjustment layer 405 is exposed and gate openings 410 are defined. Through the steps described above, the structure illustrated in FIG. 4C is formed.
Next, the D-FET gate opening 410 is covered using a photoresist mask (not illustrated), and then the exposed threshold adjustment layer 405 in the E-FET gate opening is removed through selective wet-etching using hydrochloric acid etchant by using the insulating film 409 as a mask, so that the donor layer 404 is exposed and a gate opening 411 is defined. Through the steps described above, the structure illustrated in FIG. 4D is formed.
Next, gate metal made of WSi is deposited over the entire surface through a spattering method, and then removed, leaving portions to be gate electrodes, through dry-etching using a photoresist mask (not illustrated), so that the E-FET gate electrode 412 and the D-FET gate electrode 413 are formed. Through the steps described above, the structure illustrated in FIG. 4E is formed.
Next, openings in which ohmic electrodes are to be formed are defined in the insulating film 409 by using a photoresist mask (not illustrated), and the ohmic electrodes 414 made of AuGeNi are formed through a vacuum evaporation and lift-off method.
Through the steps described above, the structure of the conventional semiconductor device 400 illustrated in FIG. 3 is formed.
With the above-described conventional techniques, however, it is difficult to control the threshold voltage (hereinafter referred to as Vth) in the E-FET, and there is a further problem that forward voltage (hereinafter referred to as Vf) of the gate decreases.
With the semiconductor device 300 disclosed in Patent reference 1, for example, an etching with nm-level accuracy needs to be performed by sequence control when removing the etching stopper layer 306. Thus, there is a concern that etching might extend even to the donor layer 304 with which the gate electrode forms a Schottky barrier junction depending on conditions such as material or film thickness of the etching stopper layer 306 and the threshold adjustment layer 305. As a result, the Vth varies for each product. In other words, the controllability for the Vth, which aims to obtain a constant Vth, has a problem.
Further, in the semiconductor device 300 disclosed in Patent reference 1 and the semiconductor device 400 disclosed in Patent reference 2, the layer which forms a Schottky barrier junction with the E-FET gate electrodes 314 or 412 is the n-type GaAs donor layer 304 or 404. Thus, in the case where the gate electrode is formed on a semiconductor layer doped as n-type, the Vf decreases.
In other words, the conventional semiconductor devices which include both the E-FET and the D-FET have failed to achieve the feature and the accuracy required especially for the E-FET.